1. Field of the Invention
The present invention relates to techniques of buried wiring in semiconductor technology.
2. Description of the Related Art
With higher operation speed and higher integration density, wiring has become thinner and more multilayered. Since thinning of wiring results in an increase in resistance and a decrease in reliability, it is required to use low-resistance, high-reliability wiring materials such as Au, Ag, and Cu.
Such materials, however, have problems with respect to adhesion to an interlayer insulating film, diffusion into the interlayer insulating film, oxidation and agglomeration, as compared to conventional Al-based materials.
In order to solve these problems, when this kind of material is used, the periphery of wiring is coated with a film of a material different from the material of the wiring. This kind of wiring is formed, for example, by a process illustrated in FIGS. 1A to 1D.
As is shown in FIG. 1A, at first, a semiconductor substrate 201, on the surface of which an interlayer insulating film 202 is formed, is prepared. A barrier metal layer 203, having effects in preventing diffusion of material wiring and enhancing adhesion, is formed on the interlayer insulating film 202 by means of vapor deposition or sputtering. A conductor 204, which will become wiring, is formed on the barrier metal layer 203. A barrier metal layer 205 having the same effects as the barrier metal layer 203 is formed on the conductor film 204. A resist is coated on the barrier metal layer 205, exposed, and developed, thereby forming a resist pattern 206 for forming wiring.
Then, as shown in FIG. 1B, with the resist pattern 206 used as a mask, the barrier metal layer 205, conductor film 204 and barrier metal layer 203 are etched in a shape of wiring.
Subsequently, as shown in FIG. 1C, a barrier metal layer 207, which is different from the wiring 204 and has the same effects as the barrier metal layer 203, is formed on the entire resultant structure, thereby covering side walls of the wiring portion.
Lastly, as shown in FIG. 1D, the barrier metal layer 207 is anisotropically etched, thereby selectively leaving the barrier metal layer 207 on the side walls of the wiring portion.
According to this process, since the wiring structure wherein the outer surfaces of the conductor film 204 or wiring body is coated with barrier metal layers 203, 205 and 207 is obtained, oxidation and diffusion of the wiring material can be prevented.
This process, however, has the following problems: the number of steps is large, and the insulating film provided on the wiring must be flattened, and thus this process is not suitable for multilayer structure.
If the wiring portion obtained in the step shown in FIG. 1B is formed in a tapered shape, the barrier metal layer 207 may not be formed on the side walls of the wiring portion, as shown in FIG. 2A, or the conductor film 207 on the side walls of the wiring portion may be etched at the time of the anisotropic etching, as shown in FIG. 2B, and, as a result, the side walls of the wiring portion are not coated with the barrier metal layer 207. Thus, the oxidation and diffusion of the wiring material cannot be prevented.
FIGS. 3A and 3B are cross-sectional views showing steps of another conventional wiring forming process.
At first, as shown in FIG. 3A, wiring 208 made of an alloy of a wiring material and a material tending to be oxidized or nitrided more easily than the wiring material is formed on a semiconductor substrate 201 on which an interlayer insulating film 202 is provided.
Then, the structure shown in FIG. 3A is annealed in an atmosphere including a slight quantity of oxygen or nitrogen. As a result, as shown in FIG. 3B, the above-mentioned material tending to be oxidized or nitrided more easily is diffused to the surfaces of the wiring 208, and an oxide film or a nitride film 209 is formed on the entire periphery of the wiring 208. Since the oxide film or nitride film 209 is formed, the impurity concentration in the wiring 208 decreases and the interior of the wiring 208 has properties similar to a pure metal.
This process, however, has the following problems. High-temperature heat treatment is required to form the oxide film or nitride film 209. Because of this, transistor characteristics are adversely effected. For example, the depth of a junction increases. Moreover, since an intergranular diffusion is dominant with respect to the diffusion, it is difficult to coat the wiring 208 uniformly with the oxide film or nitride film 209. These problems lead to degradation in reliability.
FIGS. 4A to 4D are cross-sectional views showing steps of another conventional wiring forming process.
As is shown in FIG. 4A, an interlayer insulating film 202 having a wiring groove in a surface portion thereof is formed on a semiconductor substrate 201.
A diffusion prevention layer 210 is formed on the entire structure, as shown in FIG. 4B, thereby to prevent a wiring material from diffusing into the interlayer insulating film 202. Subsequently, a conductor layer 211 which will become a buried wiring portion is formed on the entire structure. The material of the diffusion prevention film 210 is, for example, a material tending to be oxidized or nitrided more easily than the wiring material.
Then, as shown in FIG. 4C, the entire surface of the resultant structure is etched so as to leave the conductor film 211 only in the wiring groove, thus forming the buried wiring portion 211.
Lastly, as shown in FIG. 4D, the resultant structure is annealed in an atmosphere including a slight amount of oxygen or nitrogen, and diffusion is effected in a region from the diffusion prevention film 210 up to the surface of the buried wiring portion 211. Thus, an oxide film or nitride film 212 is formed in a surface portion of the buried wiring 211.
According to this method, since the surface of the wiring 211 can be coated with the oxide film or nitride film 212 in a self-alignment manner, the number of steps is not increased.
However, since the intergranular diffusion is dominant with respect to the diffusion, the oxide film or nitride film 212 is not formed uniformly although the conductor film 211 is not alloyed. Therefore, there is a problem in reliability.
In addition, like the process illustrated in FIGS. 3A and 3B, high-temperature heat treatment is required to form the oxide film or nitride film 212. The high-temperature heat treatment adversely affects transistor characteristics and requires completeness of the diffusion prevention film 210.
Furthermore, since the width of the wiring 211 is decreased by the degree corresponding to the presence of the diffusion prevention film 210, the wiring resistance increases. If the width of the wiring groove is enlarged, the problem of wiring resistance does not occur. However, because of the increase in width of the wiring groove, the wiring cannot be thinned effectively.
FIGS. 5A to 5D are cross-sectional views showing steps of a process for forming a through-hole in buried wiring. A wiring groove and a through-hole are formed in this order. In this invention, "through-hole" refers to a via hole for connection between wiring layers or a contact hole for connection between a wiring layer and a semiconductor substrate.
At first, as shown in FIG. 5A, a first interlayer insulating film 221 and a second interlayer insulating film 222 are formed on the semiconductor substrate 220 in this order. Then, a wiring groove 223 is formed in the second interlayer insulating film 222.
Subsequently, as shown in FIG. 5B, a resist pattern 224 for forming the through-hole is provided. In this case, the resist pattern 224 is displaced to the right owing to misalignment.
With the resist pattern 224 used as a mask, the first interlayer insulating film 221 is etched to form a through-hole 225, as shown in FIG. 5C.
Since the resist pattern 224 is displaced a predetermined portion of the first interlayer insulating film 221 remains unetched while a non-predetermined portion of the second interlayer insulating film 222 is etched.
Thus, as shown in FIG. 5D, a contact area of the through-hole 225 decreases by a degree corresponding to displacement of the resist pattern 224, and the width of the wiring groove 223 increases at the through-hole 225.
The decrease in contact area of the through-hole 225 leads to an increase in contact resistance and a degradation in shape of a contact electrode at the through-hole, resulting in degradation in reliability. On the other hand, the increase in width of the wiring prevents an increase in integration density.
FIGS. 6A to 6D are cross-sectional views showing steps of another process for forming a through-hole in buried wiring. In this process, a through-hole is formed prior to a wiring groove.
At first, as shown in FIG. 6A, a first interlayer insulating film 221 and a second interlayer insulating layer 222 are formed in this order on a semiconductor substrate 220, and that portion of the second interlayer insulating film 222, where the through-hole will be formed, is etched.
A resist pattern 226 for forming a wiring groove is provided on the entire structure, as shown in FIG. 6B. In this case, the resist pattern 226 is displaced to the right owing to misalignment.
With the resist pattern 226 used as a mask, the first and second interlayer insulating films 221 and 222 are etched. Thereby, a wiring groove 223 and a through-hole 225 are simultaneously formed.
Since the resist pattern 226 is displaced, that portion of the first interlayer insulating film 221, at which the through-hole should be formed, is not etched.
Like the preceding process, the contact area of the through-hole 225 decreases, as shown in FIG. 6D, and the width of the wiring groove 223 increases at the through-hole 225. Consequently, the same problem as mentioned above occurs.
FIGS. 7A to 7F are cross-sectional views showing steps of a conventional wiring forming process in the case where an underlayer includes a stepped portion.
At first, as is shown in FIG. 7A, a field oxide film 402 is formed on a semiconductor substrate 401. Then, a gate oxide film 404, a gate electrode 405 and a diffusion layer 403 are formed. Thereafter, an interlayer insulating film 406 is formed on the entire structure.
By means of a CMP method or an etch-back method, the surface of the interlayer insulating film 406 is flattened.
Subsequently, as shown in FIG. 7C, through-holes 407a and 407b are formed by means of photolithography. In this case, the depth of the through-hole 407b formed in the region of the gate electrode 405 is less than the through-hole 407a formed in the region of the diffusion layer 403 by a degree corresponding to the total thickness of the field oxide film 402, gate oxide film 404 and gate electrode 405.
In the next step shown in FIG. 7D, contact layers 408a and 408b made of a metal such as W are selectively formed in the through-holes by means of selective CVD method so that the deeper through-hole may be filled with the contact layer 408a. In this case, the contact layer 408b formed in the shallower through-hole is overfilled from the through-hole.
The contact layer 408b overfilled from the through-hole is etched away, as shown in FIG. 7E, thereby flattening the contact layer 408b.
Lastly, as shown in FIG. 7F, wirings 409a and 409b are formed on the contact layers 408a and 408b.
This wiring forming process, however, as the problem.
Since the contact layers buried in the through-holes differ in thickness, the contact layers in the through-holes differ in resistance and reliability. Moreover, a stepped portion is created by the wirings 409a and 409b and the flatness of the surface is not obtained.
If the contact layers 408a and 408b are formed so that the shallower through-hole may be filled with the contact layer 408b, as shown in FIG. 8A, a stepped portion is created in the deeper through-hole. If wiring is formed in this state, unevenness appears in the surface of the wiring formed in the deeper through-hole, as shown in FIG. 8B.
Whether the contact layers are formed so that the deeper through-hole may be filled or the shallower through-hole may be filled, surface unevenness occurs and it becomes difficult to flatten an interlayer insulating film to be formed in a later step.
FIGS. 9A to 9D are cross-sectional views showing steps of another conventional wiring forming process in the case where an underlayer includes a stepped portion.
At first, as is shown in FIG. 9A, a field oxide film 402 is formed on a semiconductor substrate 401. Then, a diffusion layer 403, a gate oxide film 404, a gate electrode 405 and an interlayer insulating film 406 are formed.
In the next step shown in FIG. 9B, through-holes 407a and 407b are formed on the diffusion layer 403 and gate electrode 405. In this case, since the interlayer insulating film 406 is not flattened, the two through-holes 407a and 407b are equal in size.
As is shown in FIG. 9C, a metal is selectively deposited in the through-holes, for example, by selective CVD, thereby forming contact layers 408a and 408b.
Wiring portions 409a and 409b are formed on the contact layers 408a and 408b, as shown in FIG. 9D.
According to this process, since the through-holes 407a and 407b are equal in depth, the contact layers in the through-holes are equal in resistance and reliability at any portions.
However, since the interlayer insulating film 406 is not flattened, a focus error, etc. occurs at the time of forming a resist pattern for forming the wiring portions 409a and 409b. It is thus difficult to form wirings 409a and 409b of desired dimensions.
Furthermore, since the wiring portions 409a and 409b are formed on the non-flat interlayer insulating film 406, it becomes more difficult to flatten an interlayer insulating film to be formed in a later step.
In the meantime, in order to reduce a parasitic capacitance due to an interlayer insulating film, it is conventionally adopted to dope the interlayer insulating film with a dopant such as fluorine.
Such an interlayer insulating film, however, has the problems: high water absorption properties, a film quality rending to deteriorate easily, and a tendency of outward diffusion of a dopant in the interlayer insulating film.
To solve these problems, it is necessary to coat the entire periphery of this kind of interlayer insulating film with a film of a material different from the material of the interlayer insulating film. Such an interlayer insulating film can be formed by the following process.
At first, as shown in FIG. 10A, a first non-doped interlayer insulating film 412 is deposited on a semiconductor substrate 411, and a doping interlayer insulating film 413 of a low dielectric constant, in which fluorine is doped, is deposited on the first non-doped interlayer insulating film 412. Subsequently, a second non-doped interlayer insulating film 414 is deposited on the doping interlayer insulating film 413.
According to the thus obtained interlayer insulating film of the sandwich structure, water absorption and outward diffusion of fluorine in the doping interlayer insulating film 413 can be prevented by the first and second non-doped interlayer insulating films 412 and 414.
The interlayer insulating film of the sandwich structure, however, has the following problems.
Even if the doping interlayer insulating film 413 of a low dielectric constant is formed, the film 413 is sandwiched by the non-doped interlayer insulating films 412 and 414 of relatively high dielectric constants. Thus, the capacitance of the entire insulating films is relatively large, which influences the operation speed of the device.
As is shown in FIG. 10B, if a through-hole is formed in the interlayer insulating films, the side surfaces of the doping interlayer insulating film 413 are exposed. In particular, water is absorbed from the exposed side surfaces and the reliability is degraded. In order to solve these problems, it may be considered to evaporate water by annealing. In this case, however, the number of steps increases.
As described above, when a low-resistance, high-reliability wiring material such as Au, Ag or Cu is used, the entire periphery of the wiring needs to be coated with a film of a material different from the material of the wiring, thereby to prevent diffusion into the interlayer insulating film and oxidation.
In order to form a wiring structure wherein a wiring portion is coated with a film of a material different from the material of the wiring, there have been proposed a method in which the top and bottom of wiring are sandwiched by films of a material different from the wiring material and then films of the different material is left on the side walls of the wiring, and a method in which diffusion from a film of a different material to the surface of the wiring is utilized.
In the case of the former, however, the number of steps increases, the wiring may not be coated in a predetermined manner, or a multilayer structure is not advantageously obtained, resulting in low reliability.
On the other hand, in the case of the latter, since the wiring can be coated in a self-alignment manner, the number of steps does not increase. However, high-temperature heat treatment is required for diffusion. The high-temperature heat treatment adversely affects transistor characteristics and degrades the reliability.
The conventional process of forming the through-hole in the buried wiring has the following problem: since the misalignment of the resist pattern for forming the wiring groove and through-hole cannot be corrected completely, the contact area of the through-hole decreases, resulting in an increase in contact resistance, degradation in shape of a contact electrode, and degradation in reliability.
In the case where the underlayer has a stepped portion, as mentioned above, the interlayer insulating film with a stepped portion on its surface is formed.
If the interlayer insulating film is flattened and contact holes are formed on regions at different levels, the through-holes differ in depth from each other. It is thus difficult to form a good contact layer.
On the other hand, if through-holes are formed without flattening the interlayer insulating film, the through-holes are equal in depth. However, the flatness of the interlayer insulating film is not good, it becomes very difficult to flatten another interlayer insulating film formed in a later step.
Besides, as described above, a dopant such as fluorine is conventionally doped in the interlayer insulating film in order to reduce a parasitic capacitance of the interlayer insulating film. This kind of doping interlayer insulating film, however, tends to absorb water easily. To solve this problem, the top and bottom of the doping interlayer insulating film are sandwiched by non-doped interlayer insulating films and thus an interlayer insulating film of a sandwich structure is used.
In the interlayer insulating film of the sandwich structure, however, the dielectric constant of the insulating film between the non-doped interlayer insulating films is low, but the capacitance of the entire interlayer insulating films is relatively great, which influences the operation speed of the device.
If the through-hole is formed in the interlayer insulating films, the side surfaces of the doping interlayer insulating film are exposed. Water is absorbed from the side surfaces and the reliability deteriorates. In order to solve this problem, it may be considered to evaporate water by annealing. In this case, however, the number of steps increases.